A Xilinx Kintex UltraScale XCVU060 FPGA with 4GB DDR4 RAM memory provides a very high performance DSP core for demanding applications such RADAR and wireless IF generation. The close integration of the analog I/O, memory and host interface with the FPGA enables real-time signal processing at rates exceeding 7000 GMAC/s.
The module supports two groups of 8-lane high-speed serial links connected to the host (one on XMC connector J15, and one on J16). These links can support several protocols (PCIe and Aurora, by default).
The XU family can be fully customized using VHDL and MATLAB and the FrameWork Logic toolset. The MATLAB BSP supports real-time hardware- in-the-loop development using the graphical, block diagram Simulink environment with Xilinx System Generator. IP logic cores are also available for SDR applications that provide multi-channel modulations for PSK and FSK systems. These IP cores transform the XU-AWG module into versatile transmitter, ready for integration into your application.
Software tools for host development include C libraries and drivers for Windows and Linux. Application examples demonstrating the module features and use are provided, including streaming DAC samples from disk. The XU-AWG can be used with the Andale high speed data record/playback system for arbitrary waveform generation from recorded data at sustained rates exceeding 7000 MB/s.A Xilinx Virtex UltraScale XCVU060 FPGA with 4GB DDR4 RAM memory (may increase to 8GB as footprint compatible higher density memories when they are validated with and supported by the FPGA) provides a very high performance DSP core for demanding applications such RADAR and wireless IF generation. The close integration of the analog IO, memory and host interface with the FPGA enables real-time signal processing at rates exceeding 7000 GMAC/s.
The XU XMC modules couple Innovative’s powerful Velocia architecture with two high performance 8-lane PCI Express links connected to the carrier, and a new XMC carrier which connects the 8 lane XU-AWG links to the 16-lane carrier PCIe link using a PCIe switch, contact the factory for availability). Alternate protocol 8-lane links to a host are also supported by the XU-AWG’s hardware using either P15’s or P16’s link to a compatible host.
The XU family can be fully customized using VHDL and MATLAB and the FrameWork Logic toolset. The MATLAB BSP supports real-time hardware- in-the-loop development using the graphical, block diagram Simulink environment with Xilinx System Generator.
IP logic cores are also available for SDR applications that provide multi-channel modulations for PSK and FSK systems. These IP cores transform the XU-AWG module into versatile transmitter, ready for integration into your application.
Software tools for host development include C libraries and drivers for Windows and Linux. Application examples demonstrating the module features and use are provided, including streaming DAC samples from disk. The XU-AWG can be used with the Andale high speed data record/playback system for arbitrary waveform generation from recorded data at sustained rates exceeding 7000 MB/s.
