The XA-AWG is an XMC IO module featuring eight 16-bit, 250 MSPS DAC channels designed for cellular base stations, diversity transmit, and wideband communications.
Flexible trigger methods include counted frames, software triggering and external triggering. The sample ate clock is either an external clock or on-board programmable PLL clock source.
Data acquisition control, signal processing, buffering, and system interface functions are implemented in a Xilinx Artix-7 FPGA device. Two 256Mx16 memories provide data buffering and FPGA computing memory.
The Artix-7 FPGA device firmware can be fully customized using VHDL and/or Xilinx System Generator along with the FrameWork Logic toolset
The PCI Express 2.0 interface supports data rates up to 1600 MB/s for unbuffered continuous data or burst data streams. When using a standard configuration
involving DDR3 buffered data, a continuous data rate up to 1600 MB/s is supported.
